1. Field of the invention
The present invention relates to an apparatus for retiming high speed digital data, in which, in binary data bits transmitted at a high speed, the data can be retimed in a stable manner, even if there are present a static skew due to a delay difference between the retiming clock pulse and the data and a dynamic skew due to the characteristic variation according to time and temperature.
2. Description of the prior art
In the conventional digital system in which data are transmitted at a high speed, there are many cases in which the total system operates in synchronization with system clock pulse. In these cases, if the phases of the data and the clock pulse are not proper (that is, if the edges of the data and the edges of the clock pulse are not separated enough to satisfy the set-up time of a flip flop and a delay time), then a metastability condition occurs, and consequently, the data cannot be retimed in a stable manner.
In an attempt to solve the above described problem, a method for recovering clock pulse based on PLL (phase locked loop) structure has been developed, as can be found in C. P. Summer (British Patent 8,039,874), M. Belkin (U.S. Pat. No. 4,400,667), and C. R. Hogge (U.S. Pat. No. 4,535,459)!. Based on this method, the data can be retimed in a stable manner during a high speed data transmission. However, its constitution is generally complicated, and there are used analogue components such as a voltage controlled oscillator, a low pass filter and the like. Therefore, it is difficult to achieve a high density, and it is uneconomical.
In an attempt to overcome the above described disadvantages, another method has been proposed. According to this method, external clock pulse having 4 phases (0.degree., 90.degree., 180.degree. and 270.degree.) is generated to detect the edge portion of the data. Then, by utilizing this, a control signal is formed to select a delay data suitable for the phases of the external pulse, from among the data having sequential phase delays. In this method, however, since the clock pulse having four phases is used, the generation of the pulses becomes difficult as the frequency becomes high R. R. Cordell (IEEE journal of solid state circuits, vol 23, No. 2, 1988)!.
In order to solve this problem, only clock pulse having phases opposite to the phases of the external clock pulse is used to reduce the number of the clock pulse having different phases. In this case, since clock pulse having inverted phases is used, the timing margin of the system is reduced, and therefore, the overall operating frequency of the system is lowered R. R. Cordell (U.S. Pat. 4,821,296)!. In order to improve this, clock pulse having a plurality of phases is generated by utilizing a delay device, so that external clock pulse having a single phase may be used S. W. Lowery (U.S. Pat. No. 5,278,873)!.
FIG. 1 illustrates the constitution of the above described conventional binary data retiming apparatus. In this drawing, reference code 101 indicates an edge detector, 102 indicates an increment-decrement controller, and 103 indicates a D/DD register & multiplexer. The edge detector 101 delays the external clock pulse by using a delaying device which has many steps. Thus, external clock pulse having a plurality of phases is generated, and by utilizing these, data edges are detected. The increment-decrement controller 102 utilizes the edge detecting signals of the detected data so as to generate up/down control signals for controlling the D/DD register & multiplexer 103. The D/DD register & multiplexer 103 receives the up/down control signals for selecting data synchronized with the phase of the external clock pulse, the selected data being outputted through a multiplexer.
The above described method has the advantage that the clock pulse having a plurality of phases is not required. That is, it uses clock pulse of a single phase. However, like the methods described before above, the non-periodical random data are delayed by using a delaying device, and therefore, the system performance becomes data-pattern-dependent. Therefore, if the data phases show a continuous difference more than a certain period of time so as to depart (wander) from a predetermined delay limit, then an initialization has to be carried out. Therefore, a data loss is generated, and due to this, the system falls into a fault state.